For more than three decades, the continued miniaturization of metal oxide semiconductor field effect transistors (MOSFETs) has driven the worldwide semiconductor industry. Various impediments to continued scaling have been predicted for decades, but a history of innovation has sustained Moore's Law in spite of many challenges. However, there are growing signs today that metal oxide semiconductor transistors are beginning to reach their traditional scaling limits. Since it has become increasingly difficult to improve MOSFETs and therefore complementary metal oxide semiconductor (CMOS) performance through continued scaling, the development of further methods for improving performance, in addition to scaling, has become critical. One such method involves providing strained channels for the CMOS circuits, using SiGe implant anneal buffer (IAB) and strain relaxed buffer (SRB) technologies.
LAB/SRB layers are thus currently considered as being technology contenders for future development of small geometry semiconductor devices to enable an ability to provide FINFETs having different channel materials and different channel strain on the same substrate. After a relaxed top SiGe layer is formed strained Si could be grown on the relaxed top SiGe layer to form an nFET. In order to form a pFET device a higher percentage (of Ge) strained SiGe could be grown on the relaxed top SiGe layer.
However, a problem that can arise with respect to this fabrication process relates to a high defect density that can be present at the surface of the IAB/SRB layer.